Synthesis, STA, Physical Design(PD) + Demo on Cadence Tools

Synthesis, STA, Physical Design(PD) + Demo on Cadence Tools | Udemy [Update 02/2025]
English | Size: 11.2 GB
Genre: eLearning

ASIC flow, Synthesis, STA, Genus tool flow, Tempus flow, Innovus flow Physical design, Physical Verification

What you’ll learn
ASIC Flow in brief
Logical Synthesis vs Physical Synthesis
Timing Concepts, definitions
Static Timing Analysis (STA)
Timing paths, Contraints, modes
Synthesis example execution with Genus tool
STA example execution with Tempus tool
Physical design flow using Innovus tool
Floorplan
Placement
Clock Tree Synthesis (CTS)
Routing

Section 1: Synthesis and Static Timing Analysis (STA)

This course is intended for all levels of students, who want to gain knowledge in ASIC synthesis and STA.

Electronics students, who want to internships, Engineers who want to start career in VLSI field.

The course covers the following chapters:

1. ASIC flow in brief

2. Logical synthesis Part 1 – inputs and outputs of synthesis, synthesis constraints, Libraries

3. Logic Synthesis Part II – Synthesis demo using Cadence Genus tool flow

4. Physical Synthesis – Various file formats and descriptions, Physical dimensions of gates

5. Timing concepts – Setup time, hold time, slack. violations, timing budgets

6. Static Timing Analysis –

7. Timing paths – Clock to output, propagation delay, input delay, output delay etc, STA using Cadence Tempus tool flow

8. Timing constraints and various modes – MMMC

9. Timing Exceptions – False path, multi cycle path

Section 2: Physical Design

10. Inputs to Physical Design

11. Innovus Tool Steps

12. Floorplan

13. Floorplan demo

14. Placement

15. CTS

16. CTS Demo

17. Routing

18. SDC_MMMC_PVT Corners

19. Physical Verification

This course is intended for all levels of students, who want to gain knowledge in ASIC synthesis and STA.

Electronics students, who want to internships, Engineers who want to start career in VLSI field.

The course covers the following chapters:

All the topics are elaborated with detailed examples, illustrated with diagrams, where required.

Clear explanation; assignments added at the end of the course for practicing hands on examples.

The lecture is given by hands on practitioners from the VLSI industry, who have worked on multiple projects and taped out chips

For best take away from the course, kindly do hands on using tools (may be available in your institutions/companies).

All the best – Happy learning

Who this course is for:
Internship – BE/BTech/MTech students and Engineers with ECE/EEE background
Beginners who wants to start VLSI career in ASIC backend activities

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